A gate in a semiconductor device acts as a capacitor, separating source/drain terminals. Controlling the charge on the gate controls the current flow between the source/drain regions. The conventional method of constructing a gate follows the general steps of: defining active device regions on a silicon substrate, growing a gate oxide on the substrate, depositing a layer of doped polysilicon on the gate oxide, and then depositing a conductive layer (generally a refractory metal or metal silicide) on the polysilicon. Gates are then defined using a photolithographic mask and etch. In conventional processing the gate oxide layer acts as an etch stop in the unexposed portions of the mask. Etching creates gate stacks by selectively removing the material in the unexposed areas. This process exposes a cross section of the device layers on the side walls of each gate stack. Source/drain regions are then implanted into the active regions on either side of the gate stack which are covered by the remaining thin gate oxide. A reoxidation step, referred to as poly reoxidation, follows to replace the screen oxide which is stripped off after source/drain implant. During poly reoxidation a new oxide is grown over the source/drain regions and on the sidewalls of the gate. During the reoxidation step the quality of the conductive layer and the profile of the gate stack may, however, be compromised. This results from sidewall oxidation forming a bird's beak under the polysilicon edge.
One method of preventing gate stack degradation is to form a protective oxidation barrier on the side walls of the gate stack. While this method of preventing gate stack degradation protects the metal layers of the gate stack, in conventional processing the gate oxide left over from the gate etch is relied upon to serve as an etch stop for the nitride spacer dry etch. Overetching of the gate oxide layer is therefore a potential problem. It increases the risk, especially for a thin gate oxide process, of compromising the quality of the silicon surface in underlying active regions, such as source/drain regions. Another disability of this method is that, because the nitride spacers overlie the entire sidewall surface of the gate, the source/drain reoxidation has to depend upon the oxidant to diffuse through the gate oxide layer beneath the gate and nitride spacers. As a result the desired oxidation of the polysilicon gate corner may be retarded. One partial solution was to use H.sub.2 SO.sub.4 boiling to undercut the TiN (see D. H. Lee, K. H. Yeom, M. H. Cho, N. S. Kang and T. E. Shim, Gate Oxide Integrity (GOI) of MOS transistore with W/TiN stacked gate, pages 208-209, 1996 Symposium on VLSI Technology Digest of Technical Papers). Lee's approach was to prevent direct contact between the gate electrode with the patterned edge by undercutting the TiN.
Device dimensions continue to shrink for reasons such as improved device performance and increased circuit density. Smaller dimensions require thinner layers. As one example, current 4-megabit dynamic random access memories (DRAMs) typically use gate oxide layers having a thickness within a range of 200 to 250 .ANG. for both memory array and peripheral transistors. For 16-megabit DRAMs, this figure is expected to fall to 150 to 200 .ANG.; and for 64-megabit and 256-megabit DRAMs, the thickness is expected to fall still further. For electrically-programmable memories such as electrically-erasable programmable read-only memories (EEPROMs) and flash memories, even thinner gate oxide layers are required to facilitate Fowler-Nordheim tunneling (universally used as the erase mechanism and often as the write mechanism). For the current generation of 4-megabit flash memories, 110 .ANG.-thick gate oxide layers are the norm. For future generations of more dense flash memories, gate oxide layers are expected to drop to the 80 to 90 .ANG. range. As gate oxide layers become thinner, it becomes increasingly important that such layers be defect free in order to eliminate leakage. Conventional gate etching uses the gate oxide layer as an etch stop. The increasingly thin gate oxide layer requires increased selectivity in the gate etch step in order to minimize the risk of compromising the quality of the gate oxide. A defect-free, very thin, high-quality oxide without contamination is essential for proper device operation. As a result, conventional processes experience, for example, higher production costs due to higher device failures and smaller process volumes.